DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 192

• Manufacturer Part Number: DF2328BVF25V
• Description: IC H8S MCU FLASH 256K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2328BVF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: HD64F2328BVF25V

Section 6 Bus Controller
Bit 7—TP Cycle Control (TPC): Selects whether a 1-state or 2-state precharge cycle (T
used when areas 2 to 5 designated as DRAM space are accessed.
Bit 7
TPC
0
1
Bit 6—Burst Access Enable (BE): Selects enabling or disabling of burst access to areas 2 to 5
designated as DRAM space. DRAM space burst access is performed in fast page mode.
Bit 6
BE
0
1
Bit 5—RAS Down Mode (RCDM): When areas 2 to 5 are designated as DRAM space and
access to DRAM is interrupted, RCDM selects whether the next DRAM access is waited for with
the RAS signal held low (RAS down mode), or the RAS signal is driven high again (RAS up
mode).
Bit 5
RCDM
0
1
Bit 4—Reserved: Only 0 should be written to this bit.
Bits 3 and 2—Multiplex Shift Count 1 and 0 (MXC1, MXC0): These bits select the size of the
shift to the lower half of the row address in row address/column address multiplexing for the
DRAM interface. In burst operation on the DRAM interface, these bits also select the row address
to be used for comparison.
Rev.6.00 Sep. 27, 2007 Page 160 of 1268
REJ09B0220-0600
Description
1-state precharge cycle is inserted
2-state precharge cycle is inserted
Description
Burst disabled (always full access)
For DRAM space access, access in fast page mode
Description
DRAM interface: RAS up mode selected
DRAM interface: RAS down mode selected
(Initial value)
(Initial value)
(Initial value)
P
) is to be