DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 473

• Manufacturer Part Number: DF2328BVF25V
• Description: IC H8S MCU FLASH 256K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2328BVF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: HD64F2328BVF25V

10.1
The chip has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels.
10.1.1
• Maximum 16-pulse input/output
• Selection of 8 counter input clocks for each channel
• The following operations can be set for each channel:
• Buffer operation settable for channels 0 and 3
• Phase counting mode settable independently for each of channels 1, 2, 4, and 5
• Cascaded operation
• Fast access via internal 16-bit bus
⎯ A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3,
⎯ TGRC and TGRD for channels 0 and 3 can also be used as buffer registers
⎯ Waveform output at compare match: Selection of 0, 1, or toggle output
⎯ Input capture function: Selection of rising edge, falling edge, or both edge detection
⎯ Counter clear operation: Counter clearing possible by compare match or input capture
⎯ Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously
⎯ PWM mode: Any PWM output duty can be set
⎯ Input capture register double-buffering possible
⎯ Automatic rewriting of output compare register possible
⎯ Two-phase encoder pulse up/down-count possible
⎯ Channel 2 (channel 5) input clock operates as 32-bit counter by setting channel 1 (channel
⎯ Fast access is possible via a 16-bit bus interface
and two each for channels 1, 2, 4, and 5), each of which can be set independently as an
output compare/input capture register
Simultaneous clearing by compare match and input capture possible
Register simultaneous input/output possible by counter synchronous operation
Maximum of 15-phase PWM output possible by combination with synchronous operation
4) overflow/underflow
Overview
Features
Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.6.00 Sep. 27, 2007 Page 441 of 1268
Section 10 16-Bit Timer Pulse Unit (TPU)
REJ09B0220-0600