HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 91

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.6
2.6.1
The CPU has five processing states: reset, exception processing, bus release, program execution
and power-down. Figure 2.4 shows the transitions between the states.
When an internal power-on
reset by WDT or internal manual reset by
WDT occurs
Interrupt sources generated
or DMAC/DTC address
error occurs*
Note:
*
Enabled only in masked ROM version and ROM less version. Disabled in F-ZTAT version and emulator.
Processing States
State Transitions
Bus request
generated
Bus release state
From any state
when RES = 0
Figure 2.4 Transitions between Processing States
Sleep mode
Bus request
cleared
Bus request
cleared
Power-on reset state
Bus request
generated
Bus request
generated
Bus request
cleared
SSBY bit cleared
for SLEEP
instruction
processing
Exception
Program execution state
source
occurs
processing state
RES = 1
From any state when
RES = 1, MRES = 0,
Exception
RES = 0
Exception
processing
ends
Rev.4.00 Mar. 27, 2008 Page 45 of 882
RES = 1,
MRES = 1
Manual reset state
Software standby mode
SSBY bit set
for SLEEP
instruction
REJ09B0108-0400
Reset state
Power-down state
NMI or IRQ interrupt
source occurs
2. CPU