HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 743

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.3.1
The instruction register (SDIR) is a 16-bit register that can be read, but not written to, by the CPU.
H-UDI instructions can be transferred to SDIR from TDI by serial input. SDIR can be initialized
by the TRST signal, but is not initialized in software standby mode.
Instructions transferred to SDIR must be 4 bits in length. If an instruction exceeding 4 bits is input,
the last 4 bits of the serial data will be stored in SDIR.
Bit
15
14
13
12
11 to 0 ⎯
Bit Name
TS3
TS2
TS1
TS0
Instruction Register (SDIR)
Initial value R/W Description
1
1
1
1
All 0
R
R
R
R
R
Test Set Bit
0xxx: setting prohibited
100x: setting prohibited
1010: H-UDI interrupt
1011: setting prohibited
110x: setting prohibited
1110: setting prohibited
1111: BYPASS mode
[Legend]
X:
Reserved
These bits are always read as 0. The write value should
always be 0.
Don’t care
Rev.4.00 Mar. 27, 2008 Page 697 of 882
22. User Debugging Interface (H-UDI)
REJ09B0108-0400