HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 492

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13. Serial Communication Interface (SCI)
Rev.4.00 Mar. 27, 2008 Page 446 of 882
REJ09B0108-0400
Figure 13.16 Sample SCI Transmission Operation in Clocked Synchronous Mode
Synchroniza-
tion clock
Serial data
TDRE
TEND
Write transmit data to TDR and
clear TDRE flag in SSR to 0
Clear TE bit in SCR to 0
Read TDRE flag in SSR
Read TEND flag in SSR
TXI interrupt
request
generated
All data transmitted?
Start transmission
Figure 13.17 Sample Serial Transmission Flowchart
Initialization
TDRE = 1
TEND = 1
<End>
Yes
Yes
Yes
Data written to TDR
and TDRE flag cleared
to 0 in TXI interrupt
processing routine
Bit 0
Transfer
direction
Bit 1
1 frame
No
No
No
[3]
[2]
[1]
Bit 7
TXI interrupt
request
generated
[1] SCI initialization:
[2] SCI status check and transmit data
[3] Serial transmission continuation
Bit 0
Set the TxD pin using the PFC.
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DMAC or
DTC is activated by a transmit data
empty interrupt (TXI) request and data
is written to TDR.
Bit 1
Bit 6
TEI interrupt
request
generated
Bit 7