HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 582

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14. I
ASD
SCL
BC2–BC0
IRIC
(operation
example)
11. Points for caution of clearing the IRIC flag when the wait function is used
Rev.4.00 Mar. 27, 2008 Page 536 of 882
REJ09B0108-0400
While the wait function is used in I
exceeds the specified value or if a slave device in which a wait can be inserted by driving SCL
low is used, read SCL in the following way to confirm that SCL has become low, and then
clear the IRIC flag.
If the IRIC flag is cleared to 0 with WAIT = 1 while SCL is extending the high level period,
the SDA level may change before SCL becomes low, generate a start or stop condition
erroneously.
2
C Bus Interface (IIC) Option
If the IRIC flag-clear is delayed due to the interrupt or other processes and the value of BC
counter is turned to 1 or 0, please confirm the SCL pins are in L’ state after the counter
value of BC2 through BC0 is turned to 0, and clear the IRIC flag. (See figure 14.32.)
SDA
IRIC
SCL
A
9
0
Figure 14.33 Timing for Clearing IRIC Flag When WAIT = 1
Figure 14.32 IRIC Flag Clear Timing on WAIT Operation
1
7
IRIC flag clear available
SCL is detected as low
2
VIH
6
Transmit/receive data
3
[1] Decision on whether or not
5
SCL is low
Secure period in which SCL is high
4
4
2
C bus interface master mode, if the rise time of SCL
5
3
6
IRIC flag clear unavailable
2
7
1
8
[2] IRIC clear
SCL =
‘L’ confirm
IRIC flag clear available
0
A
IRIC clear
9
Transmit/receive
1
7
data
2
6
When BC2-0 ≥ 2
IRIC clear
3
5