HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 204
HD64F7144F50V
Manufacturer Part Number
HD64F7144F50V
Description
IC SUPERH MCU FLASH 256K 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Specifications of HD64F7144F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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9. Bus State Controller (BSC)
9.7
When a read from a slow device is completed, data buffers may not go off in time, causing conflict
with the next access data. If there is a data conflict during memory access, the problem can be
solved by inserting a wait in the access cycle.
To enable detection of bus cycle starts, waits can be inserted between access cycles during
continuous accesses of the same CS space by negating the CSn signal once.
9.7.1
Wait cycles are inserted in the following cases so that the number of idle cycles specified with the
IW31 to IW00 bits are inserted:
• The write cycle to the same CS space continues after the cycle read
• The continuous access is made to the different CS space after the read access
If there are idle cycles between the access cycles, the number of wait cycles is inserted that is
obtained by subtracting the existing idle cycles from the number of idle cycles specified.
Figure 9.7 shows the example of idle cycle insertion. In this example, when one idle cycle
insertion is specified between CSn space cycles, the specified one idle cycle is inserted when the
write access is performed to the CSm space immediately after the read cycle of the CSn space.
Rev.4.00 Mar. 27, 2008 Page 158 of 882
REJ09B0108-0400
Waits between Access Cycles
Prevention of Data Bus Conflicts
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