HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 155

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.4
Break on CPU Instruction Fetch Cycle
1. Register settings: UBARH = H'0000
2. Register settings: UBARH = H'0015
3. Register settings: UBARH = H'0003
Conditions set:
A user break interrupt will occur before the instruction at address H'00000404. If it is possible
for the instruction at H'00000402 to accept an interrupt, the user break exception processing
will be executed after execution of that instruction. The instruction at H'00000404 is not
executed. The PC value saved is H'00000404.
Conditions set:
A user break interrupt does not occur because the instruction fetch cycle is not a write cycle.
Conditions set:
A user break interrupt does not occur because the instruction fetch was performed for an even
address. However, if the first instruction fetch address after the branch is an odd address set by
these conditions, user break interrupt exception processing will be carried out after address
error exception processing.
Examples of Use
UBARL = H'0404
UBBR = H'0054
UBCR = H'0000
Address: H'00000404
Bus cycle: CPU, instruction fetch, read
(operand size is not included in conditions)
Interrupt requests enabled
UBARL = H'389C
UBBR = H'0058
UBCR = H'0000
Address: H'0015389C
Bus cycle: CPU, instruction fetch, write
(operand size is not included in conditions)
Interrupt requests enabled
UBARL = H'0147
UBBR = H'0054
UBCR = H'0000
Address: H'00030147
Bus cycle: CPU, instruction fetch, read
(operand size is not included in conditions)
Interrupt requests enabled
Rev.4.00 Mar. 27, 2008 Page 109 of 882
7. User Break Controller (UBC)
REJ09B0108-0400