HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 545

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11. Read the ACKB bit in ICSR.
12. Clear the IRIC flag to 0.
Note:
Data should not be
written to ICDR.
Confirm that the slave device returns acknowledgement (ACKB bit is 0). When there is still
data to be transmitted, go to step 9 to continue the next transmission. When the slave device
does not return acknowledgement (ACKB bit is set to 1), follow step 12 to end transmission.
Write 0 to the ACKE bit in ICCR, to clear the received ACKB bit to 0.
Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high,
and generates the stop condition.
User processing
(Slave output)
(Master output)
(Master output)
Figure 14.8 An Example of the Timing of Operations in Master Transmit Mode
ICDRE
ICDRT
ICDRS
SDA
IRTR
IRIC
SDA
SCL
Start condition generation
(start condition issuance)
[4] Write 1 to BBSY
and 0 to SCP
generation
[5]
Interrupt
request
Address + R/W
Address + R/W
[6] ICDR write
bit 7
1
(MLS = WAIT = 0)
bit 6
2
bit 5
3
Slave address
bit 4
[6] IRIC clear
4
bit 3
5
Rev.4.00 Mar. 27, 2008 Page 499 of 882
bit 2
6
bit 1
14. I
7
R/W
bit 0
[9] ICDR write
2
8
C Bus Interface (IIC) Option
generation
[7]
A
Interrupt
request
9
REJ09B0108-0400
Data 1
Data 1
bit 7
[9] IRIC clear
1
Data 1
bit 6
2