HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 596
HD64F7144F50V
Manufacturer Part Number
HD64F7144F50V
Description
IC SUPERH MCU FLASH 256K 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Specifications of HD64F7144F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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15. A/D Converter
15.4.3
In single-cycle scan mode , A/D conversion is to be performed once on the specified channels.
Operations are as follows.
1. When the ADST bit in ADCR is set to 1 by a software, MTU, or external trigger input, A/D
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1.
4. After A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter
15.4.4
The A/D converter has a built-in sample-and-hold circuit for each module. The A/D converter
samples the analog input when the A/D conversion start delay time (t
bit in ADCR is set to 1, then starts conversion. Figure 15.2 shows the A/D conversion timing.
Table 15.3 shows the A/D conversion time.
As indicated in figure 15.2, the A/D conversion time (t
(t
conversion time therefore varies within the ranges indicated in table 15.3.
In scan mode, the values given in table 15.3 apply to the first conversion time. The values given in
table 15.4 apply to the second and subsequent conversions.
Rev.4.00 Mar. 27, 2008 Page 550 of 882
REJ09B0108-0400
SPL
conversion starts on the channel with the lowest number in the group (AN0, AN1, ..., AN3).
the A/D data register corresponding to each channel.
If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends.
enters the idle state. When the ADST bit is cleared to 0 during A/D conversion, A/D
conversion stops and the A/D converter enters the idle state.
). The length of t
Single-Cycle Scan Mode
Input Signal Sampling and A/D Conversion Time
D
varies depending on the timing of the write access to ADCR. The total
CONV
) includes t
D
D
) has passed after the ADST
and the input sampling time
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