HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 474

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13. Serial Communication Interface (SCI)
13.4.2
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the
basic clock as shown in figure 13.3. Thus the reception margin in asynchronous mode is given by
formula (1) below.
Where M: Reception margin (%)
Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin is given by formula
below.
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
Rev.4.00 Mar. 27, 2008 Page 428 of 882
REJ09B0108-0400
Internal basic
clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
M =
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
Figure 13.3 Receive Data Sampling Timing in Asynchronous Mode
0.5 –
2N
1
0
–
8 clocks
(D – 0.5)
Start bit
N
16 clocks
7
– (L – 0.5) F
× 100%
15 0
............................ Formula (1)
D0
7
15 0
D1