HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 717

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.6.1
Table 19.4 shows the boot mode operations between reset end and branching to the programming
control program.
1. When boot mode is used, the flash memory programming control program must be prepared in
2. The SCI1 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1
3. When the boot program is initiated, the chip measures the low-level period of asynchronous
4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the
5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area
6. Before branching to the programming control program, the chip terminates transfer operations
7. Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at
8. Do not change the MD pin input levels in boot mode.
9. All interrupts are disabled during programming or erasing of the flash memory.
the host beforehand. Prepare a programming control program in accordance with the
description in section 19.8, Flash Memory Programming/Erasing.
stop bit, and no parity.
SCI communication data (H'00) transmitted continuously from the host. The chip then
calculates the bit rate of transmission from the host, and adjusts the SCI1 bit rate to match that
of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be
pulled up on the board if necessary.
completion of bit rate adjustment. The host should confirm that this adjustment end indication
(H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could
not be performed normally, initiate boot mode again by a reset. Depending on the host's
transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between
the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate
and system clock frequency of this LSI within the ranges listed in table 19.5.
H'FFFFE800 to H'FFFFFFFF is the area to which the programming control program is
transferred from the host. The boot program area cannot be used until the execution state in
boot mode switches to the programming control program.
by SCI1 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value
remains set in BRR. Therefore, the programming control program can still use it for transfer of
write data or verify data with the host. The TxD pin is high. The contents of the CPU general
registers are undefined immediately after branching to the programming control program.
These registers must be initialized at the beginning of the programming control program, as the
stack pointer (SP), in particular, is used implicitly in subroutine calls, etc.
least 25 states, and then setting the mode (MD) pins. Boot mode is also cleared when a WDT
overflow occurs.
Boot Mode
Rev.4.00 Mar. 27, 2008 Page 671 of 882
19. Flash Memory (F-ZTAT Version)
REJ09B0108-0400