HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 585

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14. Points for cautions when reading ICDR in transmit mode and writing to ICDR in receive mode
15. Points for cautions on ACKE and TRS bits in slave mode
14.5.1
IIC is enabled or disabled using the module stop control register. IIC is disabled with the initial
value. Cancelling module stop mode allows the register to be accessed. For details, see section 24,
Power-Down Modes.
When ICDR is read in transmit mode (TRS = 1) or ICDR is written to in receive mode (TRS =
0), the SCL pin may not be held low in some cases after transmit/receive operation has been
completed, thus inconveniently allowing clock pulses to be output on the SCL bus line before
ICDR is accessed correctly. To access ICDR correctly, read the ICDR after setting to receive
mode or write to the ICDR after setting to transmit mode.
In the I
mode (TRS = 1) and then the address is received in slave mode without performing appropriate
processing, interrupt handling may start at the rising edge of the 9th cycle of the clock even
when the address does not match.
Similarly, in slave mode, if the start condition or address is transmitted from the master device
in transmit mode (TRS = 1), the IRIC flag may be set as a result of the ICDRE flag set or
receiving 1 as the acknowledge bit value (ACKB = 1), thus causing an interrupt source to
occur even when the address does not match.
To use the I
⎯ When 1 is received as the acknowledge bit value for the final transmit data at the end of a
⎯ Set to receive mode (TRS = 0) before the next start condition is input in slave mode.
series of transmit operations, clear the ACKE bit in ICCR once to initialize the ACKB bit
to 0.
Complete transmit operation by the procedure shown in figure 14.23, in order to switch
from slave transmit mode to slave receive mode.
Module Stop Mode Setting
2
C bus interface, if 1 is received as the acknowledge bit value (ACKB = 1) in transmit
2
C bus interface module in slave mode, be sure to follow the procedures below.
Rev.4.00 Mar. 27, 2008 Page 539 of 882
14. I
2
C Bus Interface (IIC) Option
REJ09B0108-0400