HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 578

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14. I
Notes: 1. Apply one or more of the following measures to satisfy the I
7. Points for caution when reading ICDR at the end of master reception
Rev.4.00 Mar. 27, 2008 Page 532 of 882
REJ09B0108-0400
To halt the reception of data after a receive operation in the master receive mode has been
completed, set the TRS bit to 1 and write 0 to BBSY and SCP. By doing so, the level on SDA
will be changed from low to high while SCL is high, that is, the stop condition will be
generated. The received data can be read by reading ICDR. If there is data in the buffer,
however, the data received in ICDRS cannot be transferred to ICDR (ICDRR). Therefore, the
second-byte of data cannot be read.
When reading of the second-byte of data is required, set the stop condition in the master
receive mode (with the TRS bit being 0). When reading the received data, confirm that the
BBSY bit in ICCR is 0, the stop condition has been generated, and the bus is released. After
that, read the ICDR register while TRS is 0.
In this case, if an attempt is made to read the received data (data in ICDR) during the period
from the execution of the instruction (write 0 to BBSY and SCP of ICCR) that sets the stop
condition and the actual generation of the stop condition, it is not possible to generate the clock
correctly for a the subsequent master transmission.
Rewriting of the I
transmission/reception, such as clearing of the MST bit after the completion of
transmission/reception by the master, must not take place in any period other than period (a)
(after confirming that the BBSY bit in ICCR has been cleared to 0) in figure 14.29.
2
C Bus Interface (IIC) Option
2. When the IICX bit is 1. When the IICX bit is 0, (t
3. Calculated from the I
The values in the above table are changed by the setting of the IICX bit and the CKS2
specification.
• Ensure that the interval between the setting of the start condition and of the stop
• Adjust the rise and fall times by changing the values of the pull-up resistors and load
• Adjust the system by decreasing the transfer rate.
• Select a slave device with an input timing that permits the I/O timing.
to CKS0 bits. Since the maximum transfer rate may not be achievable, depending on
the frequency, check whether or not the I
the actual conditions that are set.
ns/min.)
condition is sufficient.
capacitance.
2
C control bit to change the mode of operation or setting of
2
C bus specifications (standard 4700 ns/min, high-speed: 1300
2
C bus interface specification is satisfied under
SCLL
−6t
Pcyc
).
2
C bus interface