HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 420

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.
Output Level Control/Status Register (OCSR): The output level control/status register (OCSR)
is a 16-bit readable/writable register that controls the enable/disable of both output level
comparison and interrupts, and indicates status. If the OSF bit is set to 1, the high current pins
become high impedance.
Rev.4.00 Mar. 27, 2008 Page 374 of 882
REJ09B0108-0400
Bit
15
14 to
10
9
Multi-Function Timer Pulse Unit (MTU)
Bit Name
OSF
⎯
OCE
0
0
Initial value
All 0
R/W
R/(W)*
R
R/W
Output Level Compare Enable
Description
Output Short Flag
This flag indicates that any one pair of the three
pairs of 2 phase outputs compared have
simultaneously become low level outputs.
[Clearing condition]
•
[Setting condition]
•
Reserved
These bits are always read as 0. The write value
should always be 0.
This bit enables the start of output level
comparisons. When setting this bit to 1, pay
attention to the output pin combinations shown in
table 11.43, Mode Transition Combinations. When 0
is output, the OSF bit is set to 1 at the same time
when this bit is set, and output goes to high
impedance. Accordingly, bits 15 to 11 and bit 9 of
the port E data register (PEDR) are set to 1. For the
MTU output comparison, set the bit to 1 after setting
the MTU's output pins with the PFC. Set this bit only
when using pins as outputs.
When the OCE bit is set to 1, if OIE = 0 a high-
impedance request will not be issued even if OSF is
set to 1. Therefore, in order to have a high-
impedance request issued according to the result of
the output level comparison, the OIE bit must be set
to 1. When OCE = 1 and OIE = 1, an interrupt
request will be generated at the same time as the
high-impedance request: however, this interrupt can
be masked by means of an interrupt controller
(INTC) setting.
0: Output level compare disabled
1: Output level compare enabled; makes an output
high impedance request when OSF = 1.
By writing 0 to OSF after reading an OSF = 1
When any one pair of the three 2-phase outputs
simultaneously become low level