HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 537

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
1
0
Bit Name
ICDRF0
STOPIM
Initial Value
0
0
R
R/W
R/W
Description
Receive Data Read Request Flag
Indicates the ICDR (ICDRR) state in receive mode.
0: Indicates that the data has already been read from
1: Indicates that data has been received successfully
[Setting condition]
•
[Clearing conditions]
•
•
Due to the condition B above, ICDRF is temporarily
cleared to 0 when ICDR (ICDRR) is read; however,
since data is transferred from ICDRS to ICDRR
immediately, ICDRF is set to 1 again.
Note that ICDR cannot be read successfully in transmit
mode (TRS = 1) because data is not transferred from
ICDRS to ICDRR. Read data from ICDR in receive
mode (TRS = 0) to read data in ICDR.
Stop Condition Detected Interrupt Mask
This bit enables/disables the issuing of stop-condition-
detected interrupt requests in the I
slave mode.
0: This setting enables the IRIC flag setting and the
1: This setting disables the IRIC flag setting or the
and transferred from ICDRS to ICDRR, and the data
is not read yet.
ICDR (ICDRR) or ICDR is initialized.
stop-condition-detected interrupt requests
(STOP = 1 or ESTP = 1) in the I
slave mode.
stop-condition-detected interrupt requests in the I
bus format in slave mode.
When data is received successfully and transferred
from ICDRS to ICDRR.
A. When data is received successfully while
B. When ICDR is read in receive mode after data
When ICDR (ICDRR) is read.
When 0 is written to the ICE bit.
ICDRF = 0 (at the rising edge of the 9th cycle of
the clock).
was received while ICDRF = 1.
Rev.4.00 Mar. 27, 2008 Page 491 of 882
14. I
2
C Bus Interface (IIC) Option
2
2
C bus format in the
C bus format in
REJ09B0108-0400
2
C