HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 20

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 I
14.1 Features............................................................................................................................. 468
14.2 Input/Output Pins .............................................................................................................. 470
14.3 Description of Registers.................................................................................................... 471
14.4 Operation .......................................................................................................................... 493
14.5 Usage Notes ...................................................................................................................... 528
Section 15 A/D Converter .................................................................................541
15.1 Features............................................................................................................................. 541
15.2 Input/Output Pins .............................................................................................................. 543
15.3 Register Descriptions ........................................................................................................ 544
15.4 Operation .......................................................................................................................... 549
Rev.4.00 Mar. 27, 2008 Page xviii of xliv
REJ09B0108-0400
14.3.1 I
14.3.2 Slave-Address Register (SAR)............................................................................. 472
14.3.3 Second Slave-Address Register (SARX) ............................................................. 473
14.3.4 I
14.3.5 I
14.3.6 I
14.3.7 Serial Control Register X (SCRX)....................................................................... 490
14.3.8 ICDRE Flag (Internal Flag) ................................................................................. 492
14.4.1 I
14.4.2 Initialization ......................................................................................................... 495
14.4.3 Operations in Master Transmission ..................................................................... 496
14.4.4 Operations in Master Reception........................................................................... 501
14.4.5 Operations in Slave Reception............................................................................. 509
14.4.6 Operations in Slave Transmission........................................................................ 518
14.4.7 Timing for Setting IRIC and the Control of SCL................................................. 521
14.4.8 DTC Operation .................................................................................................... 524
14.4.9 Noise Canceller.................................................................................................... 526
14.4.10 Initialization of Internal State .............................................................................. 526
14.5.1 Module Stop Mode Setting .................................................................................. 539
15.3.1 A/D Data Registers 0 to 7 (ADDR0 to ADDR7) ................................................. 544
15.3.2 A/D Control/Status Register_0, 1 (ADCSR_0, ADCSR_1) ................................ 545
15.3.3 A/D Control Register_0, 1 (ADCR_0, ADCR_1)................................................ 547
15.3.4 A/D Trigger Select Register (ADTSR) ................................................................ 548
15.4.1 Single Mode......................................................................................................... 549
15.4.2 Continuous Scan Mode ........................................................................................ 549
15.4.3 Single-Cycle Scan Mode...................................................................................... 550
15.4.4 Input Signal Sampling and A/D Conversion Time .............................................. 550
15.4.5 A/D Converter Activation by MTU ..................................................................... 552
2
2
2
2
2
2
C Bus Data Register (ICDR) ............................................................................. 471
C Bus Mode Register (ICMR)........................................................................... 474
C Bus Control Register (ICCR)......................................................................... 477
C Bus Status Register (ICSR)............................................................................ 486
C Bus Data Formats........................................................................................... 493
C Bus Interface (IIC) Option.........................................................467