HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 447

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• Smart card interface mode (when SMIF in SDCR is 1)
Bit
7
6
5
4
3
2
Bit Name
GM
BLK
PE
O/E
BCP1
BCP0
Initial Value R/W
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
GSM Mode
When this bit is set to 1, the SCI operates in GSM
mode. In GSM mode, the timing of the TEND setting is
advanced by 11.0 etu, and clock output control function
is added. For details, refer to section 13.7.7, Clock
Output Control.
When this bit is set to 1, the SCI operates in block
transfer mode. For details on block transfer mode, refer
to section 13.7.3, Block Transfer Mode.
During reception in smart card interface mode, this bit
must be set to 1.
Parity Enable (enabled only in asynchronous mode)
When this bit is set to 1, the parity bit is added to
transmit data in transmission, and the parity bit is
checked in reception. In smart card interface mode, this
bit must be set to 1.
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
For details on setting this bit in smart card interface
mode, refer to section 13.7.2, Data Format (Except for
Block Transfer Mode).
Basic Clock Pulse 1 and 0
These bits select the number of basic clock cycles in a
1-bit transfer interval in smart card interface mode.
00: 32 clocks (S = 32)
01: 64 clocks (S = 64)
10: 372 clocks (S = 372)
11: 256 clocks (S = 256)
For details, refer to section 13.7.4, Receive Data
Sampling Timing and Reception Margin. S stands for
the value of S in BRR (see section 13.3.9, Bit Rate
Register (BRR)).
13. Serial Communication Interface (SCI)
Rev.4.00 Mar. 27, 2008 Page 401 of 882
REJ09B0108-0400