HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 23

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.7 Flash Memory Emulation in RAM....................................................................................674
19.8 Flash Memory Programming/Erasing ...............................................................................676
19.9 Program/Erase Protection..................................................................................................680
19.10 PROM Programmer Mode ................................................................................................682
19.11 Usage Note........................................................................................................................682
Section 20 Mask ROM...................................................................................... 689
20.1 Usage Note........................................................................................................................689
Section 21 RAM ............................................................................................... 691
21.1 Usage Note........................................................................................................................691
Section 22 User Debugging Interface (H-UDI) ................................................ 693
22.1 Overview...........................................................................................................................693
22.2 Input/Output Pins ..............................................................................................................695
22.3 Register Description..........................................................................................................696
22.4 Operation...........................................................................................................................700
22.5 Usage Notes ......................................................................................................................704
19.6.2 Programming/Erasing in User Program Mode.....................................................673
19.8.1 Program/Program-Verify Mode ...........................................................................676
19.8.2 Erase/Erase-Verify Mode.....................................................................................678
19.8.3 Interrupt Handling when Programming/Erasing Flash Memory..........................678
19.9.1 Hardware Protection ............................................................................................680
19.9.2 Software Protection..............................................................................................681
19.9.3 Error Protection....................................................................................................681
19.11.1 Module Standby Mode Setting.............................................................................682
19.11.2 Notes when Converting the F-ZTAT Versions to the Masked-ROM
19.11.3 Notes on Flash Memory Programming and Erasing ............................................683
22.1.1 Features................................................................................................................693
22.1.2 Block Diagram .....................................................................................................694
22.3.1 Instruction Register (SDIR) .................................................................................697
22.3.2 Status Register (SDSR)........................................................................................698
22.3.3 Data Register (SDDR) .........................................................................................699
22.3.4 Bypass Register (SDBPR) ...................................................................................699
22.4.1 H-UDI Interrupt ...................................................................................................700
22.4.2 Bypass Mode........................................................................................................703
22.4.3 H-UDI Reset ........................................................................................................703
Versions ...............................................................................................................682
Rev.4.00 Mar. 27, 2008, Page xxi of xliv
REJ09B0108-0400