HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 457

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• Smart card interface mode (when SMIF in SDCR is 1)
Bit
7
6
Bit Name Initial Value
TDRE
RDRF
1
0
R/W
R/(W)* Transmit Data Register Empty
R/(W)* Receive Data Register Full
Description
Indicates whether TDR contains transmit data.
[Setting conditions]
•
•
•
[Clearing conditions]
•
•
•
Indicates that the receive data is stored in RDR.
[Setting condition]
•
[Clearing conditions]
•
•
•
•
The RDRF flag is not affected and retains its previous
value even if the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the
RDRF flag is still set to 1, an overrun error will occur
and the receive data will be lost.
Power-on reset or software standby mode
When the TE bit in SCR is 0
When data is transferred from TDR to TSR
When 0 is written to TDRE after reading TDRE = 1
When the DMAC is activated by a TXI interrupt
When the DTC is activated by a TXI interrupt and
transmit data is transferred to TDR while the
DISEL bit in DTMR of the DTC is 0
When serial reception ends normally and receive
data is transferred from RSR to RDR
Power-on reset or software standby mode
When 0 is written to RDRF after reading RDRF =
1
When the DMAC is activated by an RXI interrupt
When the DTC is activated by an RXI interrupt
and data is transferred from RDR while the DISEL
bit in DTMR of the DTC is 0
13. Serial Communication Interface (SCI)
Rev.4.00 Mar. 27, 2008 Page 411 of 882
REJ09B0108-0400