HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 111

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.2
5.2.1
Resets have the highest priority of any exception source. There are two types of resets: manual
resets and power-on resets. As table 5.5 shows, both types of resets initialize the internal status of
the CPU. In power-on resets, all registers of the on-chip peripheral modules are initialized; in
manual resets, they are not.
Table 5.5
5.2.2
Power-On Reset by RES Pin: When the RES pin is driven low, the LSI becomes to be a power-
on reset state. To reliably reset the LSI, the RES pin should be kept at low for at least the duration
of the oscillation settling time when applying power or when in software standby mode (when the
clock circuit is halted) or at least 25 t
CPU internal status and all registers of on-chip peripheral modules are initialized. See appendix A,
Pin States, for the status of individual pins during the power-on reset status.
In the power-on reset status, power-on reset exception processing starts when the RES pin is first
driven low for a set period of time and then returned to high. The CPU will then operate as
follows:
1. The initial value (execution start address) of the program counter (PC) is fetched from the
2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table.
3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0)
Type
Power-on reset
Manual reset
exception processing vector table.
of the status register (SR) are set to H'F (B'1111).
Resets
Types of Reset
Power-On Reset
Reset Status
RES
Low
High
High
Conditions for Transition to
Reset Status
WDT
Overflow MRES
—
Overflow
—
cyc
when the clock circuit is running. During power-on reset,
—
High
Low
CPU/INTC
Initialized
Initialized
Initialized
Rev.4.00 Mar. 27, 2008 Page 65 of 882
Internal Status
On-Chip
Peripheral
Module
Initialized
Initialized
Not initialized Not initialized
5. Exception Processing
REJ09B0108-0400
POE, PFC, IO
Port
Initialized
Not initialized