HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 254

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10. Direct Memory Access Controller (DMAC)
10.5.3
In this example, the on-chip A/D converter channel 0 is the transfer source and on-chip memory is
the transfer destination, and the address reload function is on.
Table 10.8 indicates the transfer conditions and the setting values of each of the registers.
Table 10.8 Transfer Conditions and Register Set Values for Transfer between A/D
When address reload is on, the SAR value returns to its initially established value every four
transfers. In the above example, when a transfer request is input from the A/D converter (A/D1),
the byte size data is first read from the H'FFFF8482 register of the A/D converter (AD1) and that
data is written to the on-chip memory address H'FFFFF000. Because a byte size transfer was
performed, the SAR and DAR values at this point are H'FFFF8429 and H'FFFFF001, respectively.
Also, because this is a burst transfer, the bus mastership remain secured, so continuous data
transfer is possible.
When four transfers are completed, if the address reload is off, execution continues with the fifth
and sixth transfers and the SAR value continues to increment from H'FFFF842B to H'FFFF842C
to H'FFFF842D and so on. However, when the address reload is on, the DMAC transfer is halted
upon completion of the fourth one and the bus mastership request signal to the CPU is cleared. At
this time, the value stored in SAR is not H'FFFF842B to H'FFFF842C, but H'FFFF842B to
H'FFFF8428, a return to the initially established address. The DAR value always continues to be
incremented regardless of whether the address reload is on or off.
Rev.4.00 Mar. 27, 2008 Page 208 of 882
REJ09B0108-0400
Transfer Conditions
Transfer source: on-chip A/D converter (A/D1)
Transfer destination: on-chip memory
Transfer count: 128 times (reload count 32 times)
Transfer source address: incremented
Transfer destination address: incremented
Transfer request source: A/D converter (A/D 1)
Bus mode: burst
Transfer unit: byte
Interrupt request generation at end of transfer
Channel priority ranking: 0 > 2 > 3 > 1
Example of DMA Transfer between A/D Converter and On-chip Memory (Address
Reload On)
Converter (A/D1) and On-chip Memory
Register
SAR_2
DAR_2
DMATCR_2
CHCR_2
DMAOR
Value
H'FFFF8428
H'FFFFF000
H'00000080
H'00085B25
H'0101