HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 773

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

24.3
24.3.1
Transition to Sleep Mode: If SLEEP instruction is executed while the SSBY bit in SBYCR = 0,
the CPU enters sleep mode. In sleep mode, CPU operation stops, however the contents of the
CPU's internal registers are retained. Peripheral functions except the CPU do not stop.
In sleep mode, data should not be accessed by the DMAC, DTC, or AUD.
Clearing Sleep Mode: Sleep mode is cleared by the conditions below.
• Clearing by the power-on reset
• Clearing by the manual reset
When the RES pin is driven low, the CPU enters the reset state. When the RES pin is driven
high after the elapse of the specified reset input period, the CPU starts the reset exception
handling.
When an internal Power-on reset by WDT occurs, sleep mode is also cleared.
When the MRES pin is driven low while the RES pin is high, the CPU shifts to the manual
reset state and thus sleep mode is cleared.
When an internal manual reset by WDT occurs, sleep mode is also cleared.
Operation
Sleep Mode
Rev.4.00 Mar. 27, 2008 Page 727 of 882
24. Power-Down Modes
REJ09B0108-0400