HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 220

IC SUPERH MCU FLASH 256K 112QFP

HD64F7144F50V

Manufacturer Part Number
HD64F7144F50V
Description
IC SUPERH MCU FLASH 256K 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheets

Specifications of HD64F7144F50V

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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10. Direct Memory Access Controller (DMAC)
Rev.4.00 Mar. 27, 2008 Page 174 of 882
REJ09B0108-0400
Bit
13
12
Bit Name
SM1
SM0
Initial Value
0
0
R/W
R/W
R/W
Description
Source Address Mode 1, 0
These bits specify increment/decrement of the DMA
transfer source address. These bit specifications are
ignored when transferring data from an external
device to address space in single address mode.
00: Source address fixed
01: Source address incremented (+1 during 8-bit
10: Source address decremented (–1 during 8-bit
11: Setting prohibited
When the transfer source is specified at an indirect
address, specify in source address register 3
(SAR_3) the actual storage address of the data you
want to transfer as the data storage address (indirect
address).
During indirect address mode, SAR_3 obeys the
SM1/SM0 setting for increment/decrement. In this
case, SAR_3’s increment/decrement is fixed at +4/–4
or 0, irrespective of the transfer data size specified
by TS1 and TS0.
transfer, +2 during 16-bit transfer, +4 during 32-bit
transfer)
transfer, –2 during 16-bit transfer, –4 during 32-
bit transfer)

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