HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 572

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14. I
14.4.9
The states on the SCL and SDA pins are fetched internally via the noise canceller. Figure 14.28 is
a block diagram of the noise canceller.
The noise canceller consists of a 2-stage latch circuit and match-detection circuit, which are
connected in series. The input signal on the SCL pin (or on the SDA pin) is sampled on the system
clock; when the two latch outputs match, the given level is then sent to the next stage. If the two
values do not match, the existing value is maintained.
14.4.10 Initialization of Internal State
This IIC module has a function for forcible initialization of its internal state if a deadlock occurs
during communication.
Initialization is executed by clearing ICE bit.
Rev.4.00 Mar. 27, 2008 Page 526 of 882
REJ09B0108-0400
SCL input signal or
SDA input signal
2
C Bus Interface (IIC) Option
Sampling clock
Noise Canceller
Figure 14.28 Block Diagram of the Noise Canceller
System clock period
D
Sampling clock
Latch
C
Q
D
Latch
C
Q
Match-detection
circuit
Internal SCL signal or
Internal SDA signal