HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 372

IC SUPERH MCU FLASH 256K 112QFP

HD64F7144F50V

Manufacturer Part Number
HD64F7144F50V
Description
IC SUPERH MCU FLASH 256K 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheets

Specifications of HD64F7144F50V

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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11.
11.7.8
If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be that in the buffer after input capture transfer.
Figure 11.76 shows the timing in this case.
Rev.4.00 Mar. 27, 2008 Page 326 of 882
REJ09B0108-0400
Multi-Function Timer Pulse Unit (MTU)
Figure 11.75
Contention between TGR Read and Input Capture
Address
Write signal
Compare match
signal
Compare match
buffer signal
Buffer register
TGR
Figure 11.76
Address
Read signal
Input capture
signal
TGR
Internal data
bus
Contention between Buffer Register Write and Compare Match
Contention between TGR Read and Input Capture
(Channels 3 and 4)
X
N
TGR read cycle
TGR write cycle
Buffer register
T1
TGR address
T1
address
M
T2
T2
M
M
N
Buffer register write data

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