HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 550

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14. I
User processing
Receive Operation with Wait:
Figure 14.13 and figure 14.14 are flowcharts that give examples of operations (WAIT = 1) in
master receive mode.
Rev.4.00 Mar. 27, 2008 Page 504 of 882
REJ09B0108-0400
Figure 14.12 An Example of the Stop Condition Issuance Timing in Master Receive Mode
(Master output)
(Master output)
(Slave output)
User processing
ICDRR
ICDRF
2
SCL
SDA
SDA
IRTR
IRIC
C Bus Interface (IIC) Option
Figure 14.11 An Example of the Timing of Operations in Master Receive Mode
(Master output)
(Master output)
(Slave output)
Master transmit mode
ICDRR
ICDRF
SCL
SDA
IRTR
SDA
IRIC
bit 1
Data 1
7
Data 2
[1] Clear TRS to 0
bit 0
[4] IRIC clear
A
8
9
A
[3]
9
[6] Set ACKB to 1
SCL is fixed low until ICDR is read
[1] IRIC clear
Master receive mode
SCL is fixed low until ICDR is read
[7] ICDR read (data 2)
(MLS = WAIT = 0, HNDS = 1)
(MLS = WAIT = 0, HNDS = 1)
bit 7
[2] ICDR read (dummy read)
bit 7
1
1
bit 6
2
bit 6
2
bit 5
bit 5
3
Data 2
Data 3
3
Data 1
Undefined
bit 4
4
bit 4
4
bit 3
5
bit 3
SCL is fixed low until stop condition is issued
5
bit 2
6
bit 2
6
bit 1
7
bit 1
7
[4] IRIC clear
bit 0
[9] IRIC clear
8
bit 0
8
SCL is fixed low until ICDR is read
[8]
A
9
[10] ICDR read (data 3)
A
[3]
9
[5] ICDR read
(data 1)
Stop condition generation
[11] Write 0 to BBSY and SCP
(stop condition instruction
bit 7
issuance)
1
Data 2
Data 1
Data 3
bit 6
2