HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 35

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 14.19 An Example of the Timing of Operations in Slave Receive Mode 2
Figure 14.20 Example: Flowchart of Operations in Slave Transmit Mode (HNDS = 0)............514
Figure 14.21 An Example of the Timing of Operations in Slave Receive Mode 1
Figure 14.22 An Example of the Timing of Operations in Slave Receive Mode 2
Figure 14.23 Example: Flowchart of Operations in Slave Transmit Mode ................................518
Figure 14.24 An Example of the Timing of Operations in Slave Transmit Mode (MLS = 0) ....520
Figure 14.25 IRIC Flag Set Timing and the Control of SCL (1) ................................................521
Figure 14.26 IRIC Flag Set Timing and the Control of SCL (2) ................................................522
Figure 14.27 IRIC Flag Set Timing and the Control of SCL (3) ................................................523
Figure 14.28 Block Diagram of the Noise Canceller ..................................................................526
Figure 14.29 Points for Caution in Reading Data Received by Master Reception .....................533
Figure 14.30 Flowchart and Timing of the Execution of the Instruction that Sets the Start
Figure 14.31 Timing for the Setting of the Stop Condition ........................................................535
Figure 14.32 IRIC Flag Clear Timing on WAIT Operation .......................................................536
Figure 14.33 Timing for Clearing IRIC Flag When WAIT = 1..................................................536
Figure 14.34 Timing for Reading ICDR and Accessing ICCR in Slave Transmit Mode ...........537
Figure 14.35 Timing for Setting TRS Bit in Slave Mode ...........................................................538
Section 15 A/D Converter
Figure 15.1 Block Diagram of A/D Converter............................................................................542
Figure 15.2 A/D Conversion Timing ..........................................................................................551
Figure 15.3 External Trigger Input Timing ................................................................................552
Figure 15.4 Definitions of A/D Conversion Accuracy ...............................................................555
Figure 15.5 Definitions of A/D Conversion Accuracy ...............................................................555
Figure 15.6 Example of Analog Input Circuit ............................................................................556
Figure 15.7 Example of Analog Input Protection Circuit ...........................................................558
Section 16 Compare Match Timer (CMT)
Figure 16.1 CMT Block Diagram...............................................................................................559
Figure 16.2 Counter Operation ...................................................................................................563
Figure 16.3 Count Timing ..........................................................................................................563
Figure 16.4 CMF Set Timing......................................................................................................564
Figure 16.5 Timing of CMF Clear by CPU ................................................................................565
Figure 16.6 CMCNT Write and Compare Match Contention.....................................................566
Figure 16.7 CMCNT Word Write and Increment Contention ....................................................567
Figure 16.8 CMCNT Byte Write and Increment Contention......................................................568
(MLS = 0, HNDS = 1)...........................................................................................513
(MLS = ACKB = 0, HNDS = 0)............................................................................516
(MLS = ACKB = 0, HNDS = 0)............................................................................517
Condition for Re-Transmission .............................................................................534
Rev.4.00 Mar. 27, 2008, Page xxxiii of xliv
REJ09B0108-0400