HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 526

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14. I
Rev.4.00 Mar. 27, 2008 Page 480 of 882
REJ09B0108-0400
Bit
1
2
C Bus Interface (IIC) Option
Bit Name
IRIC
Initial Value R/W
0
R/(W)* I
Description
The IRIC flag indicates that the I
generated an interrupt request for the CPU.
The timing with which the IRIC flag is set changes
according to the combination of the values of the FS
bit in SAR, the FSX bit in SARX and the WAIT bit in
ICMR. Refer to section 14.4.7, Timing for Setting IRIC
and the Control of SCL. In addition, the condition on
which the IRIC flag is set changes according to the
setting of the ACKE bit in ICCR.
[Setting conditions]
•
2
C Bus Interface Interrupt Request Flag
I
When the start condition is detected from the bus
line state after the start condition has been set.
(i.e., when the ICDRE flag is set to 1 for
transmission of the first frame).
When WAIT = 1, a wait is inserted between the
data bits and the acknowledge bit.
(i.e., at the falling edge of the 8th transmit/receive
clock)
When the transfer of data has been completed.
(i.e., at the rising edge of the 9th cycle of
transmit/receive clock with no wait inserted)
When a slave address is received after bus conflict
is lost.
(i.e., first frame following start condition)
When the ACKE bit is 1, and 1 is received as an
acknowledge bit.
(i.e., when the ACKB bit is set to 1).
When the AL flag is set to 1 because of a bus
conflict.
2
C bus format in master mode
2
C bus interface has