HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 445

IC SUPERH MCU FLASH 256K 112QFP

HD64F7144F50V

Manufacturer Part Number
HD64F7144F50V
Description
IC SUPERH MCU FLASH 256K 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheets

Specifications of HD64F7144F50V

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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13.3.5
SMR is used to set the SCI’s serial transfer format and select the baud rate generator clock source.
Some bit functions of SMR differ between normal serial communication interface mode and smart
card interface mode.
• Normal serial communication interface mode (when SMIF in SDCR is 0)
Bit
7
6
5
Bit Name
C/A
CHR
PE
Serial Mode Register (SMR)
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
Communication Mode
0: Asynchronous mode
1: Clocked synchronous mode
Character Length (enabled only in asynchronous
mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length. LSB-first is fixed
In clocked synchronous mode, a fixed data length of
8 bits is used.
Parity Enable (enabled only in asynchronous mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity bit is
checked in reception. For a multiprocessor format,
parity bit addition and checking are not performed
regardless of the PE bit setting.
and the MSB (bit 7) of TDR is not transmitted in
transmission.
13. Serial Communication Interface (SCI)
Rev.4.00 Mar. 27, 2008 Page 399 of 882
REJ09B0108-0400

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