HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 756

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Appendix B Register Field
TIOR0L—Timer I/O Control Register 0L
Rev.3.00 Mar. 26, 2007 Page 714 of 772
REJ09B0355-0300
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as
Bit
Initial value
Read/Write
a buffer register.
Legend: *: Don't care
Note: 1. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer
TGR0D I/O Control
:
:
:
:
0
1
IOD3
R/W
7
0
0
1
0
1
register, this setting is invalid and input capture/output compare is not
generated.
0
1
0
1
0
1
*
IOD2
R/W
0
1
0
1
0
1
0
1
0
1
*
*
6
0
TGR0D
is output
compare
register
TGR0D
is input
capture
register *
IOD1
R/W
5
0
1
TGR0C I/O Control
Legend: *: Don't care
Note: 1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer
Output disabled
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCD0 pin
Setting prohibited
0
1
0
1
0
1
IOD0
R/W
4
0
register, this setting is invalid and input capture/output compare is not
generated.
0
1
0
1
0
1
*
0
1
0
1
0
1
0
1
0
1
*
*
IOC3
R/W
TGR0C
is output
compare
register
TGR0C
is input
capture
register *
3
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
IOC2
R/W
1
H'FFD3
2
0
Output disabled
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCC0 pin
Setting prohibited
IOC1
R/W
1
0
IOC0
R/W
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
0
0
TPU0