HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 573

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

16.2
16.2.1
BCRL is an 8-bit readable/writable register that performs selection of the external bus release state
protocol, selection of the area partition unit, and enabling or disabling of WAIT pin input.
BCRL is initialized to H'3C by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Enabling or disabling of part of the on-chip ROM area can be selected by means of the EAE bit in
BCRL. For details of the other bits in BCRL, see section 6.2.5, Bus Control Register L (BCRL).
Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'01FFFF are
to be internal addresses or external addresses.
This setting is invalid in normal mode.
Note:
Bit 5
EAE
0
1
Bit
Initial value
R/W
* Reserved areas should not be accessed.
Register Descriptions
Bus Control Register L (BCRL)
Description
Addresses H'010000 to H'01FFFF are in on-chip ROM (in the H8S/2246 and
H8S/2245) or a reserved area* (in the H8S/2244, H8S/2243, H8S/2242, and
H8S/2241).
Addresses H'010000 to H'01FFFF are external addresses (external expansion mode)
or a reserved area* (single-chip mode).
:
:
:
BRLE
R/W
7
0
BREQOE
R/W
6
0
EAE
R/W
5
1
R/W
—
4
1
Rev.3.00 Mar. 26, 2007 Page 531 of 772
R/W
—
3
1
ASS
R/W
2
1
REJ09B0355-0300
R/W
Section 16 ROM
—
1
0
(Initial value)
WAITE
R/W
0
0