HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 227

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HD6412240

Manufacturer Part Number
HD6412240
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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7.2.7
The DTC enable registers comprise six 8-bit readable/writable registers, DTCERA to DTCERF,
with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or
disable DTC service for the corresponding interrupt sources.
The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode.
Bit n—DTC Activation Enable (DTCEn)
Note: n = 7 to 0
A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence
between interrupt sources and DTCE bits is shown in table 7.3, together with the vector number
generated for each interrupt controller.
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts
are masked, multiple activation sources can be set at one time by writing data after executing a
dummy read on the relevant register.
Bit n
DTCEn
0
1
Bit
Initial value
R/W
DTC Enable Registers (DTCER)
Description
DTC activation by this interrupt is disabled
[Clearing conditions]
1. When DISEL = 1 and data transfer ends
2. When the specified number of transfers end
DTC activation by this interrupt is enabled
[Holding condition]
When DISEL = 0 and the specified number of transfers have not ended
:
:
:
DTCE7
R/W
7
0
DTCE6
R/W
6
0
DTCE5
R/W
5
0
DTCE4
R/W
4
0
Rev.3.00 Mar. 26, 2007 Page 185 of 772
DTCE3
R/W
3
0
Section 7 Data Transfer Controller
DTCE2
R/W
2
0
DTCE1
R/W
REJ09B0355-0300
1
0
(Initial value)
DTCE0
R/W
0
0

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