HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 169

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

5.5.2
Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions is executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit or UI bit is set by one of these instructions, the new value
becomes valid two states after execution of the instruction ends.
5.5.3
There are times when interrupt acceptance is disabled by the interrupt controller.
The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has
updated the mask level with an LDC, ANDC, ORC, or XORC instruction.
5.5.4
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the move is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction.
Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the
following coding should be used.
5.5.5
When operating by clock input, acceptance of input to an IRQ is synchronized with the clock. In
software standby mode, the input is accepted asynchronously. For details on the input conditions,
see section 19.4.2, Control Signal Timing.
L1:
Instructions that Disable Interrupts
Times when Interrupts Are Disabled
Interrupts during Execution of EEPMOV Instruction
IRQ Interrupt
EEPMOV.W
MOV.W
BNE
R4,R4
L1
Rev.3.00 Mar. 26, 2007 Page 127 of 772
Section 5 Interrupt Controller
REJ09B0355-0300