HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 423

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HD6412240

Manufacturer Part Number
HD6412240
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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10.6
Application programmers should note that the following kinds of contention can occur in the 8-bit
timer.
10.6.1
The TMR is enabled or disabled by setting the module stop control register. In the initial state, the
TMR is disabled. After the module stop mode is canceled, registers can be accessed. For details,
see section 18, Power-Down Modes.
10.6.2
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear
takes priority, so that the counter is cleared and the write is not performed.
Figure 10.10 shows this operation.
Address
Internal write signal
Counter clear signal
TCNT
Usage Notes
Setting Module Stop Mode
Contention between TCNT Write and Clear
Figure 10.10 Contention between TCNT Write and Clear
TCNT write cycle by CPU
T1
N
TCNT address
Rev.3.00 Mar. 26, 2007 Page 381 of 772
T2
Section 10 8-Bit Timers
H'00
REJ09B0355-0300

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