HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 100

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
2.8.2
When the RES input goes low all current processing stops and the CPU enters the reset state. All
interrupts are masked in the reset state. Reset exception handling starts when the RES signal
changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details, refer to section 11,
Watchdog Timer.
Rev.3.00 Mar. 26, 2007 Page 58 of 772
REJ09B0355-0300
Notes: 1.
RES = high
Exception-handling state
Reset State
2.
Bus-released state
From any state except hardware standby mode, a transition to the reset state occurs whenever RES
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
From any state, a transition to hardware standby mode occurs when STBY goes low.
Reset state *
End of bus
request
End of
exception
handling
1
Figure 2.15 State Transitions
Bus
request
STBY = high, RES = low
External interrupt
Request for
exception
handling
Program execution
End of bus request
Bus request
state
Interrupt
request
SLEEP
instruction
with
SSBY = 1
Hardware standby mode *
SLEEP
instruction
with
SSBY = 0
Software standby mode
Power-down state
Sleep mode
2