HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 101

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

2.8.3
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address
(vector) from the exception vector table and branches to that address.
(1) Types of Exception Handling and Their Priority
Exception handling is performed for resets, interrupts, and trap instructions. Table 2.14 indicates
the types of exception handling and their priority. Trap instruction exception handling is always
accepted, in the program execution state.
Exception handling and the stack structure depend on the interrupt control mode set in SYSCR.
Table 2.14 Exception Handling Types and Priority
Notes: 1. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,
Priority
High
Low
2. Trap instruction exception handling is always accepted, in the program execution state.
Exception-Handling State
or immediately after reset exception handling.
Type of Exception
Reset
Interrupt
Trap instruction
Detection Timing
Synchronized with clock
End of instruction
execution or end of
exception-handling
sequence*
When TRAPA instruction
is executed
1
Rev.3.00 Mar. 26, 2007 Page 59 of 772
Start of Exception Handling
Exception handling starts
immediately after a low-to-high
transition at the RES pin, or
when the watchdog timer
overflows.
When an interrupt is requested,
exception handling starts at the
end of the current instruction or
current exception-handling
sequence
Exception handling starts when
a trap (TRAPA) instruction is
executed*
2
REJ09B0355-0300
Section 2 CPU