HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 483

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Serial data reception (asynchronous mode): Figure 12.7 shows a sample flowchart for serial
reception.
The following procedure should be used for serial data reception.
Note: * The case, in which the DTC automatically clears the RDRF flag, occurs only when DISEL in
No
No
DTC is 0 with the transfer counter not being 0. Therefore, the RDRF flag should be cleared
by CPU when DISEL is 1, or when DISEL is 0 with the transfer counter being 0.
Read receive data in RDR, and
clear RDRF flag in SSR to 0
PER
Figure 12.7 Sample Serial Reception Data Flowchart
Read RDRF flag in SSR
Clear RE bit in SCR to 0
Read ORER, PER, and
All data received?
FER flags in SSR
Start reception
Initialization
FER
RDRF = 1?
<End>
Yes
Yes
ORER = 1?
No
(Continued on next page)
Error processing
Yes
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Section 12 Serial Communication Interface (SCI)
[5]
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Rev.3.00 Mar. 26, 2007 Page 441 of 772
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[2] [3]
[4]
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SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
break detection:
If a receive error occurs, read the
ORER, PER, and FER flags in
SSR to identify the error. After
performing the appropriate error
processing, ensure that the
ORER, PER, and FER flags are
all cleared to 0. Reception cannot
be resumed if any of these flags
are set to 1. In the case of a
framing error, a break can be
detected by reading the value of
the input port corresponding to
the RxD pin.
SCI status check and receive
data read :
Read SSR and check that RDRF
= 1, then read the receive data in
RDR and clear the RDRF flag to
0. Transition of the RDRF flag
from 0 to 1 can also be identified
by an RXI interrupt.
Serial reception continuation
procedure:
To continue serial reception,
before the stop bit for the current
frame is received, read the
RDRF flag, read RDR, and clear
the RDRF flag to 0. The RDRF
flag is cleared automatically
when the DTC * is activated by
an RXI interrupt and the RDR
value is read.
Receive error processing and
REJ09B0355-0300