HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 338

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 16-Bit Timer Pulse Unit (TPU)
9.2.2
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode
for each channel. The TPU has three TMDR registers, one for each channel. The TMDR registers
are initialized to H'C0 by a reset, and in hardware standby mode.
TCNT operation should be stopped when making TMDR settings.
Bits 7 and 6—Reserved: Read-only bits, always read as 1.
Bit 5—Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or
TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare is not generated.
In channels 1 and 2, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be
modified.
Bit 5
BFB
0
1
Rev.3.00 Mar. 26, 2007 Page 296 of 772
REJ09B0355-0300
Channel 0: TMDR0
Bit
Initial value
R/W
Channel 1: TMDR1
Channel 2: TMDR2
Bit
Initial value
R/W
Timer Mode Register (TMDR)
Description
TGRB operates normally
TGRB and TGRD used together for buffer operation
:
:
:
:
:
:
—
—
—
—
7
1
7
1
—
—
—
—
6
1
6
1
BFB
R/W
—
—
5
0
5
0
BFA
R/W
—
—
4
0
4
0
MD3
MD3
R/W
R/W
3
0
3
0
MD2
MD2
R/W
R/W
2
0
2
0
MD1
MD1
R/W
R/W
1
0
1
0
(Initial value)
MD0
MD0
R/W
R/W
0
0
0
0