HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 569

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

15.2
15.2.1
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in
SYSCR, see section 3.2.2, System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Note: Do not clear the RAME bit to 0 when the DTC is used.
15.3
When the RAME bit is set to 1, accesses to H8S/2246, H8S/2244, and H8S/2242 addresses
H'FFDC00 to H'FFFBFF, and H8S/2245, H8S/2243, H8S/2241, and H8S/2240 addresses
H'FFEC00 to H'FFFBFF, are directed to the on-chip RAM. When the RAME bit is cleared to 0,
the off-chip address space is accessed.
Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to
and read in byte or word units. Each type of access can be performed in one state.
Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start
at an even address.
Bit 0
RAME
0
1
Bit
Initial value
R/W
Register Descriptions
System Control Register (SYSCR)
Operation
Description
On-chip RAM is disabled
On-chip RAM is enabled
:
:
:
R/W
—
7
0
—
—
6
0
INTM1
R/W
5
0
INTM0
R/W
4
0
Rev.3.00 Mar. 26, 2007 Page 527 of 772
NMIEG
R/W
3
0
—
—
2
0
REJ09B0355-0300
—
—
1
0
Section 15 RAM
(Initial value)
RAME
R/W
0
1