HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 211

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6.7
6.7.1
When the H8S/2245 Group accesses external space, it can insert a 1-state idle cycle (T
bus cycles in the following two cases: (1) when read accesses between different areas occur
consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an
idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output
floating time, and high-speed memory, I/O interfaces, and so on.
(1) Consecutive Reads between Different Areas
If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle
cycle is inserted at the start of the second read cycle. This is enabled in advanced mode.
Figure 6.20 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
Address bus
CS (area A)
CS (area B)
Data bus
RD
Idle Cycle
Operation
(a) Idle cycle not inserted
T
1
Bus cycle A
(ICIS1 = 0)
T
Figure 6.20 Example of Idle Cycle Operation (1)
2
T
Long output
floating time
3
Bus cycle B
T
1
T
2
Data
collision
Address bus
CS (area A)
CS (area B)
Data bus
Rev.3.00 Mar. 26, 2007 Page 169 of 772
RD
T
1
(b) Idle cycle inserted
Bus cycle A
(Initial value ICIS1 = 1)
T
2
Section 6 Bus Controller
T
3
REJ09B0355-0300
T
Bus cycle B
I
I
) between
T
1
T
2