HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 217

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6.8.5
When MSTPCR has been set to H'FFFF or H'EFFF and a transition has been made to sleep mode,
the external bus release function is stopped. If the external bus release function is to be used in
sleep mode, H'FFFF or H'EFFF should not be set in MSTPCR.
6.9
6.9.1
The H8S/2245 Group has a bus arbiter that arbitrates bus master operations.
There are two bus masters, the CPU and DTC, which perform read/write operations when they
have possession of the bus. Each bus master requests the bus by means of a bus request signal. The
bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a
bus request acknowledge signal. The selected bus master then takes possession of the bus and
begins its operation.
6.9.2
The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus
request acknowledge signal to the bus master making the request. If there are bus requests from
more than one bus master, the bus request acknowledge signal is sent to the one with the highest
priority. When a bus master receives the bus request acknowledge signal, it takes possession of the
bus until that signal is canceled.
The order of priority of the bus masters is as follows:
An internal bus access by an internal bus master, and external bus release, can be executed in
parallel.
In the event of simultaneous external bus release request, and internal bus master external access
request generation, the order of priority is as follows:
(High)
(High) External bus release > Internal bus master external access (Low)
Usage Note
Bus Arbitration
Overview
Operation
DTC
>
CPU
(Low)
Rev.3.00 Mar. 26, 2007 Page 175 of 772
Section 6 Bus Controller
REJ09B0355-0300