HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 503

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 12.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
Notes: When switching from transmit or receive operation to simultaneous
transmit and receive operations, first clear the TE bit and RE bit to
0, then set both these bits to 1 simultaneously.
* The case, in which the DTC automatically clears the TDRE flag or RDRF flag, occurs only when DISEL in
the corresponding DTC transfer is 0 with the transfer counter not being 0. Therefore, the corresponding flag
should be cleared by CPU when DISEL in the corresponding DTC transfer is 1, or when DISEL is 0 with the
transfer counter being 0.
No
No
No
Clear TE and RE bits in SCR to 0
Write transmit data to TDR and
Read receive data in RDR, and
Start transmission/reception
clear TDRE flag in SSR to 0
clear RDRF flag in SSR to 0
Read ORER flag in SSR
Read RDRF flag in SSR
Read TDRE flag in SSR
All data received?
Initialization
ORER = 1?
RDRF = 1?
TDRE = 1?
<End>
Yes
Yes
Yes
No
Error processing
Yes
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Section 12 Serial Communication Interface (SCI)
[4]
[5]
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Rev.3.00 Mar. 26, 2007 Page 461 of 772
[1]
[2]
[3]
[4]
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SCI initialization:
The TxD pin is designated as the
transmit data output pin, and the
RxD pin is designated as the
receive data input pin, enabling
simultaneous transmit and receive
operations.
SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
Transition of the TDRE flag from 0
to 1 can also be identified by a TXI
interrupt.
Receive error processing:
If a receive error occurs, read the
ORER flag in SSR , and after
performing the appropriate error
processing, clear the ORER flag to
0. Transmission/reception cannot be
resumed if the ORER flag is set to 1.
SCI status check and receive data
read:
Read SSR and check that the
RDRF flag is set to 1, then read the
receive data in RDR and clear the
RDRF flag to 0. Transition of the
RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
Serial transmission/reception
continuation procedure:
To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is transmitted,
read 1 from the TDRE flag to
confirm that writing is possible.
Then write data to TDR and clear
the TDRE flag to 0. Also, before the
MSB (bit 7) of the current frame is
received, finish reading the RDRF
flag, reading RDR, and clearing the
RDRF flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DTC is
activated by a transmit data empty
interrupt (TXI) request and data is
written to TDR. Also, the RDRF flag
is cleared automatically when the
DTC * is activated by a receive data
full interrupt (RXI) request and the
RDR value is read.
REJ09B0355-0300