HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 533

no-image

HD6412240

Manufacturer Part Number
HD6412240
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6412240FA13
Manufacturer:
HITACHI
Quantity:
8 831
Part Number:
HD6412240FA13V
Manufacturer:
HITACHI/日立
Quantity:
20 000
Part Number:
HD6412240FA20
Manufacturer:
HITACHI
Quantity:
12 388
Part Number:
HD6412240FA20V
Manufacturer:
LT
Quantity:
3 220
Part Number:
HD6412240FA20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD6412240TE13
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6412240TE13
Quantity:
33
Part Number:
HD6412240TE13V
Manufacturer:
RENESAS
Quantity:
15 090
Part Number:
HD6412240TE13V
Manufacturer:
RENESAS
Quantity:
1 000
Part Number:
HD6412240TE13V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 13 Smart Card Interface
Serial Data Transmission
As data transmission in smart card mode involves error signal sampling and retransmission
processing, the processing procedure is different from that for the normal SCI. Figure 13.4 shows
a flowchart for transmitting, and figure 13.5 shows the relation between a transmit operation and
the internal registers.
[1] Perform Smart Card interface mode initialization as described above in Initialization.
[2] Check that the ERS error flag in SSR is cleared to 0.
[3] Repeat steps [2] and [3] until it can be confirmed that the TEND flag in SSR is set to 1.
[4] Write the transmit data to TDR, clear the TDRE flag to 0, and perform the transmit operation.
The TEND flag is cleared to 0.
[5] When transmitting data continuously, go back to step [2].
[6] To end transmission, clear the TE bit to 0.
With the above processing, interrupt servicing or data transfer by the DTC is possible.
If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt
requests are enabled, a transmit data empty interrupt (TXI) request will be generated. If an error
occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt
requests are enabled, a transfer error interrupt (ERI) request will be generated.
The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag
set timing is shown in figure 13.6.
If the DTC is activated by a TXI request, the number of bytes set in the DTC can be transmitted
automatically, including automatic retransmission.
For details, see Interrupt Operations and Data Transfer Operation by DTC below.
Rev.3.00 Mar. 26, 2007 Page 491 of 772
REJ09B0355-0300

Related parts for HD6412240