HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 315

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Port F Data Register (PFDR)
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF
PFDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state after a manual reset, and in software standby mode.
Port F Register (PORTF)
PORTF is an 8-bit read-only register that shows the pin states. Writing of output data for the port
F pins (PF
If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F
read is performed while PFDDR bits are cleared to 0, the pin states are read.
Bit
Initial value
R/W
Bit
Initial value
R/W
Note: * Determined by state of pins PF
The input/output direction specified by PFDDR is ignored for pins PF
automatically designated as bus control outputs (AS, RD, HWR, and LWR).
For pins PF
port, while clearing the bit to 0 makes the pin an input port.
Note: Modes 2 and 6 cannot be used in the H8S/2240.
Modes 3 and 7
Setting a PFDDR bit to 1 makes the corresponding port F pin PF
the case of pin PF
Note: Modes 3 and 7 cannot be used in the H8S/2240.
7
to PF
:
:
:
:
:
:
2
to PF
0
) must always be performed on PFDR.
PF7DR
PF7
R/W
—*
R
7
7
7
0
0
, the output pin. Clearing the bit to 0 makes the pin an input port.
, setting a PFDDR bit to 1 makes the corresponding port F pin an output
PF6DR
PF6
R/W
—*
R
6
6
0
PF5DR
PF5
R/W
—*
R
5
5
0
7
to PF
PF4DR
0
PF4
—*
R/W
.
R
4
4
0
Rev.3.00 Mar. 26, 2007 Page 273 of 772
PF3DR
PF3
R/W
—*
R
3
3
0
6
PF2DR
to PF
PF2
—*
R/W
R
2
2
0
6
to PF
0
an output port, or in
PF1DR
Section 8 I/O Ports
PF1
REJ09B0355-0300
3
R/W
—*
, which are
R
1
1
0
PF0DR
7
PF0
to PF
—*
R/W
R
0
0
0
0
).