HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 195

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6.4.3
The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or
three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to
section 6.5.4, Basic Timing.
6.5
6.5.1
The basic bus interface enables direct connection of ROM, SRAM, and so on.
The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table
6.3).
6.5.2
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and when accessing external space, controls whether the
upper data bus (D
for the area being accessed (8-bit access space or 16-bit access space) and the data size.
8-Bit Access Space
Figure 6.8 illustrates data alignment control for the 8-bit access space. With the 8-bit access space,
the upper data bus (D
at one time is one byte: a word transfer instruction is performed as two byte accesses, and a
longword transfer instruction, as four byte accesses.
External Address Space Access Timing
Basic Bus Interface
Overview
Data Size and Data Alignment
15
to D
15
to D
8
) or lower data bus (D
8
) is always used for accesses. The amount of data that can be accessed
7
to D
0
) is used according to the bus specifications
Rev.3.00 Mar. 26, 2007 Page 153 of 772
Section 6 Bus Controller
REJ09B0355-0300