HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 19

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12.3.3 Multiprocessor
Communication Function
Figure 12.10 Sample
Multiprocessor Serial
Transmission Flowchart
12.3.4 Operation in
Clocked Synchronous
Mode
Figure 12.16 Sample
Serial Transmission
Flowchart
Figure 12.18 Sample
Serial Reception
Flowchart
Figure 12.20 Sample
Flowchart of
Simultaneous Serial
Transmit and Receive
Operations
Item
447
456
459
461
Page Revision (See Manual for Details)
Note * added to figure 12.10
[3] Serial transmission continuation procedure: ... Checking and
clearing of the TDRE flag is automatic when the DTC* is
activated by a transmit data empty interrupt (TXI) request, and ...
Note: * The case, in which the DTC automatically clears the
TDRE flag, occurs only when DISEL in DTC is 0 with the transfer
counter not being 0. Therefore, the TDRE flag should be cleared
by CPU when DISEL is 1, or when DISEL is 0 with the transfer
counter being 0.
Note * added to figure 12.16
[3] Serial transmission continuation procedure: ... Checking and
clearing of the TDRE flag is automatic when the DTC* is
activated by a transmit data empty interrupt (TXI) request, and ...
Note: * The case, in which the DTC automatically clears the
TDRE flag, occurs only when DISEL in DTC is 0 with the transfer
counter not being 0. Therefore, the TDRE flag should be cleared
by CPU when DISEL is 1, or when DISEL is 0 with the transfer
counter being 0.
Note * added to figure 12.18
[5] Serial reception continuation procedure: ... RDRF flag is
cleared automatically when the DTC* is activated by a receive
data full interrupt (RXI) request, and ...
Note: * The case, in which the DTC automatically clears the
RDRF flag, occurs only when DISEL in DTC is 0 with the transfer
counter not being 0. Therefore, the RDRF flag should be cleared
by CPU when DISEL is 1, or when DISEL is 0 with the transfer
counter being 0.
Note * added to figure 12.20
[5] Serial transmission/reception continuation procedure: ... Also
the RDRF flag is cleared automatically when the DTC* is
activated by a receive data full interrupt (RXI) request, and ...
Notes: When switching from transmit or receive operation to ...
* The case, in which the DTC automatically clears the TDRE
flag or RDRF flag, occurs only when DISEL in the corresponding
DTC transfer is 0 with the transfer counter not being 0.
Therefore, the corresponding flag should be cleared by CPU
when DISEL in the corresponding DTC transfer is 1, or when
DISEL is 0 with the transfer counter being 0.
Rev.3.00 Mar. 26, 2007 Page xix of xlii
REJ09B0355-0300