HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 164

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Interrupt Controller
[1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
[2] When interrupt requests are sent to the interrupt controller, a control level 1 interrupt,
[3] The I bit is then referenced. If the I bit is cleared to 0, it is not affected by the UI bit.
[4] When an interrupt request is accepted, interrupt exception handling starts after execution of the
[5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
[6] Next, the I and UI bits in CCR are set to 1. This masks all interrupts except NMI.
[7] A vector address is generated for the accepted interrupt, and execution of the interrupt
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interrupt request is sent to the interrupt controller.
according to the control level set in ICR, has priority for selection, and other interrupt requests
are held pending. If a number of interrupt requests with the same control level setting are
generated at the same time, the interrupt request with the highest priority according to the
priority system shown in table 5.4 is selected.
An interrupt request set to interrupt control level 0 is accepted when the I bit is cleared to 0. If
the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held
pending.
An interrupt request set to interrupt control level 1 has priority over an interrupt request set to
interrupt control level 0, and is accepted if the I bit is cleared to 0, or if the I bits is set to 1 and
the UI bit is cleared to 0.
When both the I bit and the UI bit are set to 1, only an NMI interrupt is accepted, and other
interrupt requests are held pending.
current instruction has been completed.
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
handling routine starts at the address indicated by the contents of that vector address.