HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 747

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HD6412240

Manufacturer Part Number
HD6412240
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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TCSR0—Timer Control/Status Register 0
TCSR1—Timer Control/Status Register 1
TCSR0
TCSR1
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Notes: 1. Only 0 can be written to bits 7 to 5, to clear these flags.
2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0.
:
:
:
:
:
:
R/(W)
R/(W)
Compare Match Flag B
CMFB
CMFB
0
1
7
0
7
0
*
*
1
1
[Clearing conditions]
• Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB
• When the DTC
[Setting condition]
Set when TCNT matches TCORB
R/(W)
R/(W)
Compare Match Flag A
CMFA
CMFA
0
1
6
0
6
0
*
*
1
1
[Clearing conditions]
• Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA
• When the DTC
[Setting condition]
Set when TCNT matches TCORA
R/(W)
R/(W)
Timer Overflow Flag
OVF
OVF
0
1
5
0
5
0
*
2
*
*
is activated by a CMIB interrupt, while DISEL bit of MRB in DTC is 0.
1
1
[Clearing condition]
Cleared by reading OVF when OVF = 1, then writing 0 to OVF
[Setting condition]
Set when TCNT overflows (changes from H'FF to H'00)
ADTE
A/D Trigger Enable (TCSR0 only)
R/W
0
1
4
0
4
1
*
2
is activated by a CMIA interrupt, while DISEL bit of MRB in DTC is 0.
A/D converter start requests by compare match A are disabled
A/D converter start requests by compare match A are enabled
Output Select
OS3
OS3
R/W
R/W
3
0
3
0
0
1
H'FFB2
H'FFB3
0
1
0
1
Rev.3.00 Mar. 26, 2007 Page 705 of 772
OS2
OS2
R/W
R/W
2
0
2
0
No change when compare match B occurs
0 is output when compare match B occurs
1 is output when compare match B occurs
Output is inverted when compare match B occurs
(toggle output)
Output Select
0
1
0
1
0
1
OS1
R/W
OS1
R/W
1
0
1
0
No change when compare match A
occurs
0 is output when compare match A
occurs
1 is output when compare match A
occurs
Output is inverted when compare
match A occurs (toggle output)
Appendix B Register Field
OS0
OS0
R/W
R/W
8-Bit Timer Channel 0
8-Bit Timer Channel 1
0
0
0
0
REJ09B0355-0300

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