HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 216

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller
6.8.4
Figure 6.23 shows the timing for transition to the bus-released state.
Rev.3.00 Mar. 26, 2007 Page 174 of 772
REJ09B0355-0300
Address bus
HWR, LWR
[1]
[2]
[3]
[4]
[5]
Data bus
BREQ
BACK
Transition Timing
Low level of BREQ pin is sampled at rise of T
BACK pin is driven low at end of CPU read cycle, releasing bus to external bus master.
BREQ pin state is still sampled in external bus released state.
High level of BREQ pin is sampled.
BACK pin is driven high, ending bus release cycle.
RD
AS
Figure 6.23 Bus-Released State Transition Timing
T
0
CPU cycle
T
Address
1
[1]
Minimum
1 state
T
2
[2]
2
state.
External bus released state
[3]
High impedance
High impedance
High impedance
High impedance
High impedance
[4]
[5]
cycle
CPU